1. Field of the Invention
The present invention generally relates to the design and testing of integrated circuits, and more particularly to a method and system for testing an array of electronic devices formed on an integrated circuit.
2. Description of the Related Art
Integrated circuits are used for a wide variety of electronic applications, from simple devices such as wristwatches, to the most complex computer systems. A microelectronic integrated circuit (IC) chip can generally be thought of as a collection of logic cells with electrical interconnections between the cells, formed on a semiconductor substrate (e.g., silicon). An IC may include a very large number of cells and require complicated connections between the cells. A cell is a group of one or more circuit elements such as transistors, capacitors, resistors, inductors, and other basic circuit elements grouped to perform a logic function. Cell types include, for example, core cells, scan cells and input/output (I/O) cells. Each of the cells of an IC may have one or more pins, each of which in turn may be connected to one or more other pins of the IC by wires. The wires connecting the pins of the IC are also formed on the surface of the chip.
For more complex designs, there are typically at least four distinct layers of conducting media available for routing, such as a polysilicon layer and three metal layers (metal-1, metal-2, and metal-3). The polysilicon layer, metal-1, metal-2, and metal-3 are all used for vertical and/or horizontal routing.
An IC chip is fabricated by first conceiving the logical circuit description, and then converting that logical description into a physical description, or geometric layout. This process is usually carried out using a “netlist,” which is a record of all of the nets, or interconnections, between the cell pins. A layout typically consists of a set of planar geometric shapes in several layers. The layout is then checked to ensure that it meets all of the design requirements, particularly timing requirements. The result is a set of design files known as an intermediate form that describes the layout. The design files are then converted into pattern generator files that are used to produce patterns called masks by an optical or electron beam pattern generator. During fabrication, these masks are used to pattern one or more dies on a silicon wafer using a sequence of photolithographic steps. The process of converting the specifications of an electrical circuit into a layout is called the physical design.
Cell placement in semiconductor fabrication involves a determination of where particular cells should optimally (or near-optimally) be located on the surface of a integrated circuit device. Due to the large number of components and the details required by the fabrication process for very large scale integrated (VLSI) devices, physical design is not practical without the aid of computers. As a result, most phases of physical design extensively use computer-aided design (CAD) tools, and many phases have already been partially or fully automated. Automation of the physical design process has increased the level of integration, reduced turn around time and enhanced chip performance. Several different programming languages have been created for electronic design automation (EDA), including Verilog, VHDL and TDML. A typical EDA system receives one or more high level behavioral descriptions of an IC device, and translates this high level design language description into netlists of various levels of abstraction.
Faster performance and predictability of responses are elements of interest in circuit designs. As process technology scales to the deep-submicron (DSM) regime, it is becoming increasingly important for the performance and reliability of IC chips and systems to understand how variations in process parameters affect the operation of an electronic device or circuit. A designer needs to model responses such as current flow with changes in voltage for transistors (I-V curves), or resistance/capacitance measurements for wiring. Device testing may further include leakage measurements across a gate, to indirectly assess the quality of an oxide material and identify potential flaws like pin holes or edge defects. Some devices such as static random-access memory (SRAM) require testing the memory elements with random fluctuations in threshold voltages to better characterize the circuit. Devices should also be stress tested, i.e., under different conditions such as varying temperatures.
One example of a circuit 10 used for such testing of an array of devices is shown in FIG. 1. The devices under test (DUTs) in circuit 10 may be, for example, transistors arranged in rows and columns. Each DUT 12 is connected to one of a plurality of column inputs 14 and one of a plurality of row inputs 16. Selectors 18 are used to transmit an output signal to a measurement unit 20, controlled by selector control logic 22. The input signals may be any parameter of interest, such as voltage or current. For example, when the DUTs are transistors, circuit 10 can provide varying input voltages and measure the current response. Selected voltage levels are injected at the desired DUT node through column and row inputs 14, 16, and the outputs of the transistors are routed through the appropriate selectors 18 to measurement unit 20. The output of measurement unit 20 is connected to a recording unit or a user interface device. I-V curves for the DUTs can be established by monitoring current responses for varying voltage inputs.
It is also useful to understand how spatial variations (i.e., devices located in different dies on a single wafer) can be affected by process parameters. While the outputs of circuit 10 provide a fair basis to characterize the response of the devices, the measurements are not completely accurate since they fail to take into consideration various effects on signal creation and transmission. Even metal wires have a very small resistance (as well as capacitance) that affects the propagation of signals in the wires. These loading effects can vary with wire length and environmental parameters such as temperature. Calibration of the measurement circuitry does not compensate for variations in the loading effects. Moreover, spatial variability in integrated circuits is becoming worse due to variations such as Leff variation, doping concentrations, spurious leakage, systematic variation due to chemical mechanical planarization, etc. Existing test structures cannot adequately account for the variability in these measurements. In order to reliably characterize the variabilities, hundreds of samples are needed, which is even more impractical given the limited number of input/output (C4) pads provided on the circuits. Prior art test systems only provide a few transistors on the kerf structure to monitor long-distance variabilities (wafer-to-wafer or die-to-die).
Circuit designers make assumptions about spatial variations of parameters which have a significant impact on product performance, but there is no reliable system for verifying these assumptions. It would, therefore, be desirable to devise an improved testing structure that can achieve high spatial resolution across many devices. It would be further advantageous if the test system could provide such resolution with nominal resource cost.